The invention relates to modular computer systems, and more particularly to interface apparatus facilitating communication between standard buses having different protocols.
The proliferation of microprocessors has produced the economic incentive and consequent trend to construct modular multimicroprocessor computer systems, where previous implementations used one high-performance processor. Such modular systems are facilitated by a bus structure, otherwise referred to as a backplane bus, to which the microprocessors, system controllers, data storage modules, input/output controllers and associated peripheral devices can be connected and through which they can communicate with one another. The main purpose of any bus structure is to allow devices connected to it to transfer data from one device to one or more of the other devices in accordance with a predetermined protocol of communication. A "standard" bus is one for which functional, electrical and mechanical requirements for interface circuits and a set of signal lines that constitute the bus are predetermined for all devices connected to the bus. A number of different standard bus structures have been defined and developed, and it is desirable that modules on one standard bus be able to communicate with devices on another standard bus, even though the various "standards" may differ considerably. Generally, the signal lines on standard backplane buses can be partitioned into logical groupings that include a data transfer bus, which includes address and data lines; an arbitration bus, which includes control acquisition lines; and a utility bus, which includes power leads and, on some buses, clock signals, initialization and failure detection lines.
The VMEbus, a standard 16/32 bit backplane bus, in addition to the aforementioned signal line groupings, defines a priority interrupt function, wherein a device on the VMEbus can request service from an interrupt handler by way of a priority interrupt bus to thereby invoke a software or firmware interrupt service routine. See "VMEbus Specification Manual" Revision C.1 (IEEE P1014/D1.2), Oct. 1985.
The Futurebus (ANSI/IEEE 896.1-1987) is a high-level standard bus in which no interrupt-handling facility is defined, but wherein event-driven data can be transmitted across the bus as messages having address and data items, just as all other types of data. Therefore, in an interface between VMEbus and Futurebus systems, an inordinate burden in the form of additional hardware is required to create the facility in the Futurebus system to recognize and service even simple interrupts, e.g. from single (interrupt) handler systems, which emanate from the VMEbus system or the interface hardware.
It is, therefore, a principle object of the invention to provide an improved interface circuit between standard bus structures in a multidevice modular data processing system.
A more specific object of the invention is to provide an improved means for signaling the occurrence of external events to devices connected to a standard bus structure having no interrupt facility.
Another object of the invention is to provide improved means for transmitting interrupt data across a Futurebus.
Still another object of the invention is to provide improved apparatus utilizing control acquisition logic in a Futurebus system to transmit interrupt data from a VMEbus to devices on the Futurebus.